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8xc151sa/sb high-performance chmos microcontroller temperature range with the commercial (standard) temperature option, the device operates over the temperature range 0 c to a 70 c. the express temperature option provides b 40 cto a 85 c device operation. proliferation options table 1 lists the proliferation options. see figure 2 for the 8xc151sa/sb family nomenclature. table 1. proliferation options 8xc151sa/sb (0 mhz 16 mhz; 5v g 10%) 80c151sb cpu-only 83c151sa 8k rom 83c151sb 16k rom 87c151sa 8k otprom 87c151sb 16k otprom process information this device is manufactured on a complimentary high-performance metal-oxide semiconductor (chmos) process. additional process and reliability information is available in intel's components quali- ty and reliability handbook (order number 210997). all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and ap- plication requirements. the intel packaging hand- book (order number 240800) describes intel's ther- mal impedance test methodology. table 2. thermal characteristics package type i ja i jc 44-lead plcc 46 c/w 16 c/w 40-pin pdip 45 c/w 16 c/w package options table 3 lists the 8xc151sa/sb packages. table 3. package information pkg. definition temperature n 44-lead plcc 0 cto a 70 c p 40-pin plastic dip 0 cto a 70 c tn 44-lead plcc b 40 cto a 85 c tp 40-pin plastic dip b 40 cto a 85 c 3
8xc151sa/sb high-performance chmos microcontroller 272814 2 figure 2. the 8xc151sa/sb family nomenclature table 4. description of product nomenclature parameter options description temperature and burn-in no mark commercial operating temperature range (0 cto70 c) with intel standard burn-in. options t express operating temperature range ( b 40 cto85 c) with intel standard burn-in. packaging options n 44-lead plastic leaded chip carrier (plcc) p 40-pin plastic dual in-line package (pdip) program memory 0 without rom/otprom options 3 rom 7 user programmable otprom process information c chmos product family 151 8-bit controller architecture device memory options sa/sb 256 bytes ram/8/16 kbyte rom/otprom or without rom/ otprom device speed 16 external clock frequency 4
8xc151sa/sb high-performance chmos microcontroller 272814 3 figure 3. 8xc151sa/sb 44-lead plcc package 5
8xc151sa/sb high-performance chmos microcontroller 272814 4 figure 4. 8xc151sa/sb 40-pin pdip and ceramic dip packages 6
8xc151sa/sb high-performance chmos microcontroller table 5. plcc/dip signal assignment arranged by functional categories address & data name plcc dip ad0/p0.0 43 39 ad1/p0.1 42 38 ad2/p0.2 41 37 ad3/p0.3 40 36 ad4/p0.4 39 35 ad5/p0.5 38 34 ad6/p0.6 37 33 ad7/p0.7 36 32 a8/p2.0 24 21 a9/p2.1 25 22 a10/p2.2 26 23 a11/p2.3 27 24 a12/p2.4 28 25 a13/p2.5 29 26 a14/p2.6 30 27 a15/p2.7 31 28 processsor control name plcc dip p3.2/int0 y 14 12 p3.3/int1 y 15 13 ea y /v pp 35 31 rst 10 9 xtal1 21 18 xtal2 20 19 input/output name plcc dip p1.0/t2 2 1 p1.1/t2ex 3 2 p1.2/eci 4 3 p1.3/cex0 5 4 p1.4/cex1 6 5 p1.5/cex2 7 6 p1.6/cex3 8 7 p1.7/cex4 9 8 p3.0/rxd 11 10 p3.1/txd 13 11 p3.4/t0 16 14 p3.5/t1 17 15 power & ground name plcc dip v cc 44 40 v cc2 12 e v ss 22 20 v ss1 1e v ss2 23, 34 e ea y /v pp 35 31 bus control & status name plcc dip p3.6/wr y 18 16 p3.7/rd y 19 17 ale/prog y 33 30 psen y 32 29 7
8xc151sa/sb high-performance chmos microcontroller table 6. signal assignments arranged by package number plcc dip name 1ev ss1 2 1 p1.0/t2 3 2 p1.1/t2ex 4 3 p1.2/eci 5 4 p1.3/cex0 6 5 p1.4/cex1 7 6 p1.5/cex2 8 7 p1.6/cex3 9 8 p1.7/cex4 10 9 rst 11 10 p3.0/rxd 12 e v cc2 13 11 p3.1/txd 14 12 p3.2/int0 y 15 13 p3.3/int1 y 16 14 p3.4/t0 17 15 p3.5/t1 18 16 p3.6/wr y 19 17 p3.7/rd y 20 18 xtal2 21 19 xtal1 22 20 v ss plcc dip name 23 e v ss2 24 21 a8/p2.0 25 22 a9/p2.1 26 23 a10/p2.2 27 24 a11/p2.3 28 25 a12/p2.4 29 26 a13/p2.5 30 27 a14/p2.6 31 28 a15/p2.7 32 29 psen y 33 30 ale/prog y 34 e v ss2 35 31 ea y /v pp 36 32 ad7/p0.7 37 33 ad6/p0.6 38 34 ad5/p0.5 39 35 ad4/p0.4 40 36 ad3/p0.3 41 37 ad2/p0.2 42 38 ad1/p0.1 43 39 ad0/p0.0 44 40 v cc 8
8xc151sa/sb high-performance chmos microcontroller signal descriptions table 7. signal descriptions signal type description multiplexed name with a15:8 2 o address lines. upper address lines for the external bus. p2.7:0 ad7:0 2 i/o address/data lines. multiplexed lower address lines and data lines p0.7:0 for external memory. ale o address latch enable. ale signals the start of an external bus prog y cycle and indicates that valid address information is available on lines a15:8 and ad7:0. an external latch can use ale to demultiplex the address from the address/data bus. cex4:0 i/o programmable counter array (pca) input/output pins. these p1.6:3 are input signals for the pca capture mode and output signals for the p1.7 pca compare mode and pca pwm mode. ea y i external access. directs program memory accesses to on-chip or v pp off-chip code memory. for ea y e 0, all program memory accesses are off-chip. for ea y e 1, an access is to on-chip rom/otprom if the address is within the range of the on-chip rom/otprom; otherwise the access is off-chip. the value of ea y is latched at reset. for devices without on-chip rom/otprom, ea y must be strapped to ground. eci i pca external clock input. external clock input to the 16-bit pca p1.2 timer. int1:0 y i external interrupts 0 and 1. these inputs set bits ie1:0 in the tcon p3.3:2 register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1 y /int0 y . if bits int1:0 are clear, bits ie1:0 are set by a low level on int1:0 y . prog y i programming pulse. the programming pulse is applied to this pin ale for programming the on-chip otprom. p0.7:0 i/o port 0. this is an 8-bit, open-drain, bidirectional i/o port. ad7:0 p1.0 i/o port 1. this is an 8-bit, bidirectional i/o port with internal pullups. t2 p1.1 t2ex p1.2 eci p1.7:3 cex3:0 cex4 p2.7:0 i/o port 2. this is an 8-bit, bidirectional i/o port with internal pullups. a15:8 2 the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0). 9
8xc151sa/sb high-performance chmos microcontroller table 7. signal descriptions (continued) signal type description multiplexed name with p3.0 i/o port 3. this is an 8-bit, bidirectional i/o port with internal pullups. rxd p3.1 txd p3.3:2 int1:0 y p3.5:4 t1:0 p3.6 wr y p3.7 rd y psen y o program store enable. read signal output. this output is asserted e for a memory address range that depends on bits rd0 and rd1 in configuration byte uconfig0. rd y o read. read signal output to external data memory. p3.7 rst i reset. reset input to the chip. holding this pin high for 64 oscillator e periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and v cc . asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. rxd i/o receive serial data. rxd sends and receives data in serial i/o p3.0 mode 0 and receives data in serial i/o modes 1, 2, and 3. t1:0 i timer 1:0 external clock inputs. when timer 1:0 operates as a p3.5:4 counter, a falling edge on the t1:0 pin increments the count. t2 i/o timer 2 clock input/output. for the timer 2 capture mode, this p1.0 signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. t2ex i timer 2 external input. in timer 2 capture mode, a falling edge p1.1 initiates a capture of the timer 2 registers. in auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up- down counter mode, this signal determines the count direction: 1 e up, 0 e down. txd o transmit serial data. txd outputs the shift clock in serial i/o mode p3.1 0 and transmits serial data in serial i/o modes 1, 2, and 3. v cc pwr supply voltage. connect this pin to the a 5v supply voltage. e v cc2 pwr secondary supply voltage 2. this supply voltage connection is e provided to reduce power supply noise. connection of this pin to the a 5v supply voltage is recommended. however, when using the 8xc151sa/sb as a pin-for-pin replacement for the 8xc51fx, v ss2 can be unconnected without loss of compatibility. (not available on dip) v pp i programming supply voltage. the programming supply voltage is ea y applied to this pin for programming the on-chip otprom. 2 the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0). 10
8xc151sa/sb high-performance chmos microcontroller table 7. signal descriptions (continued) signal type description multiplexed name with v ss gnd circuit ground. connect this pin to ground. e v ss1 gnd secondary ground. this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the 8xc151sa/sb as a pin- for-pin replacement for the 8xc51bh, v ss1 can be unconnected without loss of compatibility. (not available on dip) v ss2 gnd secondary ground 2. this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the 8xc151sa/sb as a pin-for-pin replacement for the 8xc51fx, v ss2 can be unconnected without loss of compatibility. (not available on dip) wr y o write. write signal output to external memory. p3.6 xtal1 i input to the on-chip, inverting, oscillator amplifier. to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for internal timing. xtal2 o output of the on-chip, inverting, oscillator amplifier. to use the e internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. 2 the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0). 11
8xc151sa/sb high-performance chmos microcontroller electrical characteristics absolute maximum ratings * ambient temperature under bias: commercial 0 cto a 70 c express b 40 cto a 85 c storage temperature b 65 cto a 150 c voltage on ea y /v pp pin to v ss 0v to a 13.0v voltage on any other pin to v ss b 0.5v to a 6.5v i ol per i/o pin 15 ma power dissipation1.5w note: maximum power dissipation is based on package heat-transfer limitations, not device power con- sumption. operating conditions * t a (ambient temperature under bias): commercial 0 cto a 70 c express b 40 cto a 85 c v cc (digital supply voltage) 4.5v to 5.5v v ss 0v notice: this document contains information on products in the design phase of development. do not finalize a design with this information. revised infor- mation will be published when the product is avail- able. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 12
8xc151sa/sb high-performance chmos microcontroller dc characteristics parameter values apply to all devices unless otherwise indicated. table 8. dc characteristics at v cc e 4.5v b 5.5v symbol parameter min typical max units test conditions v il input low voltage b 0.5 0.2v cc b 0.1 v (except ea y ) v il1 input low voltage 0 0.2v cc b 0.3 v (ea y ) v ih input high voltage 0.2v cc a 0.9 v cc a 0.5 v (except xtal1, rst) v ih1 input high voltage 0.7v cc v cc a 0.5 v (xtal1, rst) v ol output low voltage 0.3 v i ol e 100 m a (port 1, 2, 3) 0.45 i ol e 1.6 ma 1.0 i ol e 3.5 ma (note 1, note 2) v ol1 output low voltage 0.3 v i ol e 200 m a (port 0, ale, psen y ) 0.45 i ol e 3.2 ma 1.0 i ol e 7.0 ma (note 1, note 2) v oh output high voltage v cc b 0.3 v i oh eb 10 m a (port 1, 2, 3, ale, v cc b 0.7 i oh eb 30 m a psen y )v cc b 1.5 i oh eb 60 m a (note 3) notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0 26 ma ports 1 3 15 ma maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen y to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v cc e 5.0, t a e 25 c and are not guaranteed. 13
8xc151sa/sb high-performance chmos microcontroller table 8. dc characteristics at v cc e 4.5v b 5.5v (continued) symbol parameter min typical max units test conditions v oh1 output high voltage v cc b 0.3 v i oh eb 200 m a (port 0 in external v cc b 0.7 i oh eb 3.2 ma address) v cc b 1.5 i oh eb 7.0 ma v oh2 output high voltage v cc b 0.3 v i oh eb 200 m a (port 2 in external v cc b 0.7 i oh eb 3.2 ma address during page v cc b 1.5 i oh eb 7.0 ma mode) i il logical 0 input cur- b 50 m av in e 0.45v rent (port 1, 2, 3) i li input leakage cur- g 10 m a 0.45 k v in k v cc rent (port 0) i tl logical 1-to-0 transi- b 650 m av in e 2.0v tion current (port 1, 2, 3) r rst rst pulldown resistor 40 225 k x c io pin capacitance 10 pf f osc e 16 mhz (note 4) t a e 25 c i pd powerdown current 10 k 20 m a (note 4) i dl idle mode current 13 20 ma f osc e 16 mhz (note 4) i cc operating current 71 85 ma f osc e 16 mhz (note 4) notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0 26 ma ports 1 3 15 ma maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen y to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v cc e 5.0, t a e 25 c and are not guaranteed. 14
8xc151sa/sb high-performance chmos microcontroller 272814 5 all other 8xc151sa/sb pins are unconnected. figure 5. i pd test condition, powerdown mode, v cc e 2.0v b 5.5v 15
8xc151sa/sb high-performance chmos microcontroller ac characteristics table 8 lists ac timing parameters for the 8xc151sa/sb with no wait states. external wait states can be added by extending psen y /rd y / wr y and/or by extending ale. in the table, notes 3 and 5 mark parameters affected by an ale wait state, and notes 4 and 5 mark parameters affected by a psen y /rd y /wr y wait state. figures 5 11 show the bus cycles with the timing parameters. table 9. ac characteristics (capacitive loading e 50 pf) symbol parameter @ max f osc (1) f osc variable units min max min max f osc xtal1 frequency n/a n/a 0 16 mhz t osc 1/f osc n/a n/a ns @ 12 mhz 83.3 @ 16 mhz 62.5 t lhll ale pulse width ns @ 12 mhz 68.3 (3) @ 16 mhz 47.5 (1 a 2m) t osc b 15 t avll address valid to ale low ns @ 12 mhz 58.3 (3) @ 16 mhz 37.5 (1 a 2m) t osc b 25 t llax address hold after ale low ns @ 12 mhz 10 @ 16 mhz 10 10 t rlrh (2) rd y or psen y pulse width ns @ 12 mhz 151.6 (4) @ 16 mhz 110 2(1 a n) t osc b 15 t wlwh wr y pulse width ns @ 12 mhz 151.6 (4) @ 16 mhz 110 2(1 a n) t osc b 15 t llrl (2) ale low to rd y or psen y low ns @ 12 mhz 58.3 @ 16 mhz 37.5 tosc b 25 t lhax ale high to address hold ns @ 12 mhz 83.3 (3) @ 16 mhz 62.5 (1 a 2m) t osc notes: 1. 16 mhz. 2. specifications for psen y are identical to those for rd y . 3. in the formula, m e number of wait states (0 or 1) for ale. 4. in the formula, n e number of wait states (0, 1, 2, or 3) for rd y /psen y /wr y . 5. ``typical'' specifications are untested and not guaranteed. 16
8xc151sa/sb high-performance chmos microcontroller table 9. ac characteristics (capacitive loading e 50 pf) (continued) symbol parameter @ max f osc (1) f osc variable units min max min max t rldv (2) rd y /psen y low to valid data/instruction in ns @ 12 mhz 111.6 (4) @ 16 mhz 70 2(1 a n) t osc b 55 t rhdx (2) rd y /psen y data/instruction hold 00 ns after rd y and psen y high t rlaz (2) rd y /psen y low to address float typ. e 0 2 typ. e 02ns (5) (5) t rhdz1 instruction float after rd y /psen y high ns @ 12 mhz 0 @ 16 mhz 0 0 t rhdz2 data float after rd y /psen y high ns @ 12 mhz 151.6 @ 16 mhz 110 2t osc b 15 t rhlh1 rd y /psen y high to ale high (instruction) ns @ 12 mhz 0 @ 16 mhz 0 0 t rhlh2 rd y /psen y high to ale high (data) ns @ 12 mhz 156.6 @ 16 mhz 115 2t osc b 10 t whlh wr y high to ale high ns @ 12 mhz 166.6 @ 16 mhz 125 2t osc t avdv1 address (p0) valid to valid data/instruction in ns @ 12 mhz 253.2 (3) @ 16 mhz 170 4(1 a m/2) t osc b 80 t avdv2 address (p2) valid to valid data/instruction in ns @ 12 mhz 268.2 (3) @ 16 mhz 185 4(1 a m/2) t osc b 65 t avdv3 address (p0) valid to valid instruction in ns @ 12 mhz 116.6 @ 16 mhz 75 2t osc b 50 notes: 1. 16 mhz. 2. specifications for psen y are identical to those for rd y . 3. in the formula, m e number of wait states (0 or 1) for ale. 4. in the formula, n e number of wait states (0, 1, 2, or 3) for rd y /psen y /wr y . 5. ``typical'' specifications are untested and not guaranteed. 17
8xc151sa/sb high-performance chmos microcontroller table 9. ac characteristics (capacitive loading e 50 pf) (continued) symbol parameter @ max f osc (1) f osc variable units min max min max t avrl (2) address valid to rd y /psen y low ns @ 12 mhz 126.6 (3) @ 16 mhz 85 2(1 a m) t osc b 40 t avwl1 address (p0) valid to wr y low ns @ 12 mhz 126.6 (3) @ 16 mhz 85 2(1 a m) t osc b 40 t avwl2 address (p2) valid to wr y low ns @ 12 mhz 141.6 (3) @ 16 mhz 100 2(1 a m) t osc b 25 t whqx data hold after wr y high ns @ 12 mhz 58.3 @ 16 mhz 37.5 t osc b 25 t qvwh data valid to wr y high ns @ 12 mhz 146.6 (4) @ 16 mhz 105 2(1 a n) t osc b 20 t whax wr y high to address hold ns @ 12 mhz 146.6 @ 16 mhz 105 2t osc b 20 notes: 1. 16 mhz. 2. specifications for psen y are identical to those for rd y . 3. in the formula, m e number of wait states (0 or 1) for ale. 4. in the formula, n e number of wait states (0, 1, 2, or 3) for rd y /psen y /wr y . 5. ``typical'' specifications are untested and not guaranteed. 18
8xc151sa/sb high-performance chmos microcontroller system bus timings 272814 6 2 the value of this parameter depends on wait states. see the table of ac characteristics. figure 6. external read data bus cycle in nonpage mode 19
8xc151sa/sb high-performance chmos microcontroller 272814 7 2 the value of this parameter depends on wait states. see the table of ac characteristics. figure 7. external instruction bus cycle in nonpage mode 20
8xc151sa/sb high-performance chmos microcontroller 272814 8 2 the value of this parameter depends on wait states. see the table of ac characteristics. figure 8. external write data bus cycle in nonpage mode 21
8xc151sa/sb high-performance chmos microcontroller 272814 9 2 the value of this parameter depends on wait states. see the table of ac characteristics. figure 9. external read data bus cycle in page mode 22
8xc151sa/sb high-performance chmos microcontroller 272814 10 2 the value of this parameter depends on wait states. see the table of ac characteristics. figure 10. external write data bus cycle in page mode 23
8xc151sa/sb high-performance chmos microcontroller 272814 11 2 the value of this parameter depends on wait states. see the table of ac characteristics. 22 a page hit (i.e., a code fetch to the same 256-byte ``page'' as the previous code fetch) requires one state (2t osc ); a page miss requires two states (4t osc ). 222 during a sequence of page hits, psen y remains low until the end of the last page-hit cycle. figure 11. external instruction bus cycle in page mode 24
8xc151sa/sb high-performance chmos microcontroller ac characteristicseserial port, shift register mode table 10. serial port timing shift register mode symbol parameter min max units t xlxl serial port clock cycle time 12t osc ns t qvsh output data setup to clock rising edge 10t osc b 133 ns t xhqx output data hold after clock rising edge 2t osc b 117 ns t xhdx input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 10t osc b 133 ns 272814 12 2 ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit. figure 12. serial port waveform eshift register mode 25
8xc151sa/sb high-performance chmos microcontroller external clock drive table 11. external clock drive symbol parameter min max units 1/t clcl oscillator frequency (f osc ) 16 mhz t chcx high time 20 ns t clcx low time 20 ns t clch rise time 10 ns t chcl fall time 10 ns 272814 13 figure 13. external clock drive waveforms 272814 14 ac inputs during testing are driven at v cc b 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at a min of v ih for logic 1 and v ol for a logic 0. figure 14. ac testing input, output waveforms 26
8xc151sa/sb high-performance chmos microcontroller 272814 15 for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh e g 20 ma. figure 15. float waveforms 272814 16 figure 16. setup for programming and verifying nonvolatile memory 27
8xc151sa/sb high-performance chmos microcontroller programming and verifying nonvolatile memory the 87c151sa/sb has several areas of nonvolatile memory that can be programmed and/or verified: on-chip code memory (8/16 kbytes), lock bits (3 bits), encryption array (128 bytes), and signature bytes (3 bytes). figure 16 shows the setup for programming and/or verifying the nonvolatile memory. table 11 lists the programming and verification operations and indi- cates which operations apply to the different ver- sions of the 87c151sa/sb. it also specifies the sig- nals on the programming input (prog y ) and the ports. the rom/otprom mode (port 0) specifies the operation (program or verify) and the base ad- dress of the memory area. the addresses (ports 1 and 3) are relative to the base address. (on-chip memory for a 16-kbyte rom/otprom device is lo- cated at address range 0000h 3fffh. the other areas of the rom/otprom are outside the memo- ry address space and are accessible only during pro- gramming and verification.) information in figures 17 and 18 define the configu- ration bits. figure 19 shows the waveforms for the programming and verification cycles, and table 12 lists the timing specifications. the signature bytes of the 83c151sa/sb rom versions and the 87c151sa/sb otprom versions are factory pro- grammed. table 13 lists the addresses and the con- tents of the signature bytes. factory-programmed rom and otprom versions of 8xc151sa/sb use configuration byte information supplied in a separate hexadecimal disk file. 8xc151sa/sb devices without internal rom/otprom arrays fetch configuration byte in- formation from external application memory based on an internal address range of fff9:8h. note: the v pp source in figure 16 must be well regu- lated and free of glitches. the voltage on the v pp pin must not exceed the specified maximum, even under transient conditions. 28
8xc151sa/sb high-performance chmos microcontroller table 12. programming and verification modes mode 8xc151sa/sb addresses mode prog y p0 p2 p1 (high), p3 (low) notes x e 7x e 3 program on-chip code y 5 pulses 68h data 0000h 3fffh (16k) 1 memory 0000h 1fffh (8k) verify on-chip code y y high 28h data 0000h 3fffh (16k) memory 0000h 1fffh (8k) program configuration 2 bytes verify configuration 2 bytes program lock bits y 25 pulses 6bh xx 0001h 0003h 1, 3 verify lock bits y y high 2bh data 0000h 4 program encryption y 25 pulses 6ch data 0000h 007fh 1 array verify signature bytes y y high 29h data 0030h, 0031h, 0060h notes: 1. the prog y pulse waveform is shown in figure 19. 2. factory-programmed rom and otprom versions of 8xc151sa/sb use configuration byte information supplied in a separate hexadecimal disk file. 8xc151sa/sb devices without internal rom/otprom arrays fetch configuration byte information from external application memory based on an internal address range of fff9:8h. 3. when programming the lock bits, the data bits on port 2 are don't care. identify the lock bits with the address as follows: lb3 - 0003h, lb2 - 0002h, lb1 - 0001h. 4. the three lock bits are verified in a single operation. the states of the lock bits appear simultaneously at port 2 as follows: lb3 - p2.3, lb2 - p2.2. lb1 - p2.1. high e programmed. 29
8xc151sa/sb high-performance chmos microcontroller uconfig0 address fff8h 7 0 e wsa1 y wsa0 y xale y e e page y e bit bit function number mnemonic 7 e reserved 6:5 wsa1 y wait state select for external code wsa0 y wsa1 y wsa0 y description (see note) 1 1 no wait states 1 0 insert 1 wait state 0 1 insert 2 wait states 0 0 insert 3 wait states 4 xale y extend ale: if this bit is set, the time of the ale pulse is t osc . clearing this bit extends the time of the ale pulse from t osc to 3t osc , which adds one external wait state. 1 page y page mode select: clear this bit for page-mode (a15:8/d7:0 on p2, and a7:0 on p0). set this bit for nonpage-mode (a15:8 on p2, and a7:0/d7:0 on p0 (compatible with mcs 51 microcontrollers)). note: factory-programmed rom and otprom versions of 8xc151sa/sb use configuration byte information supplied in a separate hexadecimal disk file. 8xc151sa/sb devices without internal rom/otprom arrays fetch configuration byte information from external application memory based on an internal address range of fff9:8h. figure 17. configuration byte 0 30
8xc151sa/sb high-performance chmos microcontroller uconfig1 address fff9h 7 0 e e e e e wsb1 y wsb0 y e bit bit function number mnemonic 7:5 e reserved; set these bits when writing to uconfig1. 2:1 wsb1 y , wait states for external data wsb0 y wsb1 y wsb0 y description 1 1 no wait states 1 0 insert 1 wait state 0 1 insert 2 wait states 0 0 insert 3 wait states note: factory-programmed rom and otprom versions of 8xc151sa/sb use configuration byte information supplied in a separate hexadecimal disk file. 8xc151sa/sb devices without internal rom/otprom arrays fetch configuration byte information from external application memory based on an internal address range of fff9:8h. figure 18. configuration byte 1 31
8xc151sa/sb high-performance chmos microcontroller 272814 17 figure 19. timing for programming and verification of nonvolatile memory 32
8xc151sa/sb high-performance chmos microcontroller table 13. nonvolatile memory programming and verification characteristics at t a e 21 b 27 c, v cc e 5v, and v ss e 0v symbol definition min max units v pp programming supply voltage 12.5 13.5 d.c. volts i pp programming supply current 75 ma f osc oscillator frequency 4.0 6.0 mhz t avgl address setup to prog y low 48t osc t ghax address hold after prog y 48t osc t dvgl data setup to prog y low 48t osc t ghdx data hold after prog y 48t osc t ehsh enable high to v pp 48t osc t shgl v pp setup to prog y low 10 m s t ghsl v pp hold after prog y 10 m s t glgh prog y width 90 110 m s t avqv address to data valid 48t osc t elqv enable low to data valid 48to sc t ehqz data float after enable 0 48t osc t ghgl prog y high to prog y low 10 m s note: notation for timing parameters: a e address d e data e e enable g e prog y h e high l e low q e data out s e supply (v pp )v e valid x e no longer valid z e floating table 14. contents of the signature bytes address contents device type 30h 89h indicates intel devices 31h 48h indicates mcs 151 core product 60h 7bh indicates 83c151sb device 60h fbh indicates 87c151sb device 60h 7ah indicates 83c151sa device 60h fah indicates 87c151sa device 33

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